a. Field of the Invention
The present invention relates generally to the field of solid state circuits and more particularly to an improved electrical ladder network for use in forming decremntally weighted signals of the type used in digital to analog converters.
B. Prior Art
Weighted resistor networks may be used in many fields of application. One exemplary field is in digital to analog converters wherein a digitally coded signal comprising a plurality of ones and zeros is to be converted into an equivalent analog output. A good explanation of digital to analog converters of the prior art, including a discussion of prior art resistor networks of the type found herein, is described in the book "Analog Integrated Circuit Design" by A. Grebene, Van Nostrand, New York, 1973. The aforementioned text describes the requisites of a digital to analog converter including a reference signal, a set of binary switches which simulate binary coefficients of a number to be converted, a resistive weighting network and an output summing means. The present invention relates to the resistive weighting network used in such a converter.
FIG. 1 shows a digital to analog converter of the prior art including a resistive weighting network known as an R-2R resistor ladder. The resistor ladder of the prior art is shown within the dashed line 11. On the left hand side the network is referenced to a fixed voltage V-, while on the right hand side, the ladder terminates in line 13' connected to a terminating resistor 15 having value 2R. The prior art R- 2R ladder has a plurality of outputs 21, 22, 23, 24, 25, 26, 27, 28. It will be noted that the ladder includes resistor "rungs" of value 2R and "extensions" of value R. This combination of rungs and extensions serves to divide the current in each rung such that the current in each rung is decremented by fifty percent of the preceding rung. For example, if each output 21-28 is connected to a respective current source Q1-Q8, the current sourced by the first transistor Q1 will be twice the current sourced by the second transistor Q2 which in turn will be twice the current sourced by the third transistor Q3 and so on. Thus, if the first transistor Q1 sources 1 milliamp of current, the second transistor Q2 will source 0.5 milliamps, the third 0.25 milliamps; the fourth 0.125 ma.; the fifth, 0.062 ma; the sixth 0.031 ma; the seventh 0.016 ma; and the eight 0.008 ma; with a remainder of 0.008 ma sourced by the terminating transistor Q9.
In the prior art apparatus of FIG. 1, each of the current sources Q1-Q8 would generate an emitter voltage error for each ladder rung because a different V.sub.BE would exist for each transistor. However, to offset this the geometry of the transistors Q1-Q8 has been scaled so as to maintain the same current density through each emitter junction. Thus, the base-emitter junction of Q1 is 128 times the area of the base-emitter junction of Q8. If the base-emitter area of Q1 is designated 128x, then the remaining area for successive transistors are as follows: Q2, 64x; Q3, 32x; Q4, 16x; Q5, 8x; Q6, 4x; Q7, 2x; Q8, 1x; and Q9 also being 1x since it will be recalled that the resistive drop across the terminating resistor is to be the same as that in the last resistor. The purpose of the reference transistor QR is to translate a standard voltage reference V.sub.R into a stable current. To achieve this purpose an operational amplifier A1 has an input connected to the reference resistor RR and an output connected to the reference transistor QR as well as the remaining transistors Q1-Q9 for the purpose of supplying base current to the aforesaid transistors thereby allowing them to sink current. The reference transistor has a V.sub.BE character which is scaled to Q1 at a two-to-one relationship.
In practice, the degree of emitter scaling shown in FIG. 1 is difficult to achieve. An alternate R-2R ladder of the prior art is shown in FIG. 2. Once again a reference voltage V.sub.R is provided and is converted to a reference current by the operational amplifier A2 having the reference transistor QS in its feedback booth. Reference current is supplied to a plurality of transistors Q11, Q12, Q13, Q14, Q15, Q16, Q17 and Q18. A resistive weighting network, which is essentially the same as the weighting network 11 of FIG. 1 is shown in the dashed line 21, i.e., an R-2R resistor ladder. On the left hand side, the network is referenced to a fixed voltage V-. This combination of rungs, having resistance 2R, and extensions, having value R, serves to divide the current in the network such that the current in each rung is decremented by 50 percent of the preceding rung. The right hand side of the ladder terminates in line 23' connected to a terminating resistor 25 having value 2R. By analogy with the currents of FIG. 1, it will be seen that the ladder of FIG. 2 decrements currents in much the same way. In FIG. 2 however the terminating resistor and its associated transistor Q16 are placed in parallel with transistors Q17, Q18 which have a resistor 26 in the emitter circuit thereof, connected to the fixed voltage V-. The two transistors Q17, Q18 duplicate the current in the terminating transistor Q16 and are similarly constructed to transistor Q16. Thus, although the resistive load of the transistors Q17, Q18 is much greater than 2R, however, several R and 2R resistors have been eliminated while providing a second ladder, with a low number of resistors in series with a first ladder, of the type described with respect to FIG. 1. The problem with the second ladder circuit of FIG. 2 is that the currents therein are not decremented with respect to each of the transistors Q16, Q17 and Q18. Rather the currents drawn are the same. A further method must be applied to decrement these last currents, without adding extra transistor scaling range or many extra resistors. Thus, in FIG. 2a lower scaling range was achieved by adding extra resistors and sacrificing current decrements, resulting in an incomplete ladder circuit.
It is an object of the invention to provide a minimum scaling range, use fewest resistors, and provide an output of n decremented currents with no further circuitry needed.